The present invention relates to a packet switch for outputting packets input through an input line after allocating them to a plurality of output lines.
With an increasing number of Internet users at home and with the remarkable growth of Internet business, an Internet backbone network of a larger capacity and higher quality is strongly demanded. Currently, Internet is mainly operated in best-effort communications without quality guarantee. However, Internet in the future generation is expected to provide real time data communications using voice, video data, etc. in addition to the best-effort communications. Therefore, it is necessary for a network node to provide the service quality QoS (Quality of Service) appropriate for various communications services by acquiring a terabit switching capacity with which various types of traffic can be flexibly accommodated. It is considered that the probable means for realizing a node having a terabit switching capacity is an input buffer packet switch capable of performing a process at a high memory access speed.
Various scheduling algorithms have been conventionally suggested for input buffer packet switches. They can be roughly grouped into the following two methods based on the assignment of scheduling functions, that is, a method of distributing and assigning the scheduling functions to interface cards, etc. and a method of assigning the scheduling functions collectively to exclusive cards, etc.
FIGS. 22 and 23 show the distribution of the scheduling functions in the conventional input buffer packet switch. FIG. 22 shows the configuration of the packet switch in which the scheduling functions are distributed and fed. FIG. 23 shows the configuration of the packet switch in which the scheduling functions are collectively assigned.
As shown in FIG. 22, the input buffer packet switch in which the scheduling functions are distributed and assigned includes an interface card 100 containing an input buffer and a scheduler for each input line. The scheduling information can be transmitted and received (a notification of an undefined line can be given) among schedulers by interconnecting the schedulers in the adjacent interface cards 100, and the scheduling process can be performed for all input lines. When the number of input lines increases or decrease, the number of interface cards 100 can also be increased or decreased to be equal to the number of the input lines. Therefore, the input buffer packet switch with the configuration shown in FIG. 22 excels in extensibility.
On the other hand, as shown in FIG. 23, the input buffer packet switch in which the scheduling functions are collectively assigned includes a scheduling function section for all input lines collectively in one scheduler card 110, thereby performing a scheduling process on all input lines. Since the length of the wiring between the scheduling function sections is short, the wiring reduces a delay, and the restrictions placed by the delay time of a signal when the switch is installed can be considerably reduced.
However, since it is necessary for the conventional input buffer packet switch in which the scheduling functions are distributed and assigned to interconnect the schedulers provided in each of the installed interface cards 100, the length of the connection line causes a delay, thereby placing more restrictions when a high-speed packet switch is installed.
In the conventional input buffer packet switch in which the scheduling function sections are collectively assigned, it is necessary for the scheduler card 110 to be provided with the largest possible number of scheduling function sections even when there are a small number of the input lines actually. After installing the scheduling function sections, the number of the sections is fixed. Therefore, this switch is wasteful and poor in extensibility.